SDRAM W949D2DBJX5I, 512Mbit, 200MHZ, Montaje superficial, VFBGA, 90 pines LPDDR

VDD = 1.7∼1.95V
VDDQ = 1.7∼1.95V
Data width: x16 / x32
Clock rate: 200MHz (-5),166MHz (-6)
Standard Self Refresh Mode
Partial Array Self-Refresh(PASR)
Auto Temperature Compensated Self Refresh (ATCSR)
Power Down Mode
Deep Power Down Mode (DPD Mode)
Programmable output buffer driver strength
Four internal banks for concurrent operation
Data mask (DM) for write data
Clock Stop capability during idle periods
Auto Pre-charge option for each burst access
Double data rate for data output
Differential clock inputs (CK and CK)
Bidirectional, data strobe (DQS)
CAS Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
8K refresh cycles/64 mS
Interface: LVCMOS compatible
Support package:
60 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended: -25°C ≤ TCASE ≤ 85°C
Industrial: -40°C ≤ TCASE ≤ 85°C

This is a 512Mb Low Power DDR SDRAM organized as 2M words x 4 banks x 32bits.

Burst Type: Sequential or Interleave
Standard Self Refresh Mode
PASR, ATCSR, Power Down Mode、DPD
Programmable output buffer driver strength
Four internal banks for concurrent operation
Bidirectional, data strobe (DQS) is transmitted or received with data, to be used in capturing data at the receiver