SDRAM W9412G6KH-5I, 128Mbit, 200MHZ, Montaje superficial, TSOP, 66 pines

The W9412G6KH is a 128M DDR SDRAM and speed involving -5/-5I/-6I.

2.5V ±0.2V Power Supply for DDR400/333
2.4V∼2.7V Power Supply for DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture, two data transfers per clock cycle
Differential clock inputs (CLK and /CLK)
DQS is edge-aligned with data for Read, center-aligned with data for Write
CAS Latency: 2, 2.5, and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
15.6 μS Refresh interval (4K/64 mS Refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2